NXP Semiconductors /LPC408x_7x /RTC /ERCONTROL

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Interpret as ERCONTROL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (NO_INTERRUPT_OR_WAKE)INTWAKE_EN0 0 (NOGPREG)GPCLEAR_EN0 0 (NEG)POL0 0 (DISABLED)EV0_INPUT_EN 0RESERVED0 (NO_INTERRUPT_OR_WAKE)INTWAKE_EN1 0 (NOGPREG)GPCLEAR_EN1 0 (NEG)POL1 0 (DISABLED)EV1_INPUT_EN 0RESERVED0 (NO_INTERRUPT_OR_WAKE)INTWAKE_EN2 0 (NOGPREG)GPCLEAR_EN2 0 (NEG)POL2 0 (DISABLED)EV2_INPUT_EN 0RESERVED0 (DISABLED)ERMODE

GPCLEAR_EN2=NOGPREG, POL1=NEG, POL2=NEG, EV1_INPUT_EN=DISABLED, GPCLEAR_EN1=NOGPREG, GPCLEAR_EN0=NOGPREG, EV2_INPUT_EN=DISABLED, INTWAKE_EN1=NO_INTERRUPT_OR_WAKE, ERMODE=DISABLED, POL0=NEG, INTWAKE_EN2=NO_INTERRUPT_OR_WAKE, EV0_INPUT_EN=DISABLED, INTWAKE_EN0=NO_INTERRUPT_OR_WAKE

Description

Event Monitor/Recorder Control register. Contains bits that control actions for the event channels as well as for Event Monitor/Recorder setup.

Fields

INTWAKE_EN0

Interrupt and wakeup enable for channel 0.

0 (NO_INTERRUPT_OR_WAKE): No interrupt or wakeup will be generated by event channel 0.

1 (AN_EVENT_IN_CHANNEL_): An event in channel 0 will trigger an (RTC) interrupt and a wake-up request.

GPCLEAR_EN0

Enables automatically clearing the RTC general purpose registers when an event occurs on channel 0.

0 (NOGPREG): Channel 0 has no influence on the general purpose registers.

1 (CLRGPREG): An event in channel 0 will clear the general purpose registers asynchronously.

POL0

Selects the polarity of an event on input pin RTC_EV0.

0 (NEG): A channel 0 event is defined as a negative edge on RTC_EV0.

1 (POS): A channel 0 event is defined as a positive edge on RTC_EV0.

EV0_INPUT_EN

Event enable control for channel 0.[1]

0 (DISABLED): Event 0 input is disabled and forced high internally.

1 (ENABLED): Event 0 input is enabled.

RESERVED

Reserved. Read value is undefined, only zero should be written.

INTWAKE_EN1

Interrupt and wakeup enable for channel 1.

0 (NO_INTERRUPT_OR_WAKE): No interrupt or wakeup will be generated by event channel 1.

1 (WAKEUP): An event in channel 1 will trigger an (RTC) interrupt and a wake-up request.

GPCLEAR_EN1

Enables automatically clearing the RTC general purpose registers when an event occurs on channel 1.

0 (NOGPREG): Channel 1 has no influence on the general purpose registers.

1 (CLRGPREG): A n event in channel 1 will clear the general purpose registers asynchronously.

POL1

Selects the polarity of an event on input pin RTC_EV1.

0 (NEG): A channel 1 event is defined as a negative edge on RTC_EV1.

1 (POS): A channel 1 event is defined as a positive edge on RTC_EV1.

EV1_INPUT_EN

Event enable control for channel 1.[1]

0 (DISABLED): Event 1 input is disabled and forced high internally.

1 (ENABLED): Event 1 input is enabled.

RESERVED

Reserved. Read value is undefined, only zero should be written.

INTWAKE_EN2

Interrupt and wakeup enable for channel 2.

0 (NO_INTERRUPT_OR_WAKE): No interrupt or wakeup will be generated by event channel 2.

1 (WAKEUP): An event in channel 2 will trigger an (RTC) interrupt and a wake-up request.

GPCLEAR_EN2

Enables automatically clearing the RTC general purpose registers when an event occurs on channel 2.

0 (NOGPREG): Channel 2 has no influence on the general purpose registers.

1 (CLRGPREG): An event in channel 2 will clear the general purpose registers asynchronously.

POL2

Selects the polarity of an event on input pin RTC_EV2.

0 (NEG): A channel 2 event is defined as a negative edge on RTC_EV2.

1 (POS): A channel 2 event is defined as a positive edge on RTC_EV2.

EV2_INPUT_EN

Event enable control for channel 2.[1]

0 (DISABLED): Event 2 input is disabled and forced high internally.

1 (ENABLED): Event 2 input is enabled.

RESERVED

Reserved. Read value is undefined, only zero should be written.

ERMODE

Controls enabling the Event Monitor/Recorder and selecting its operating frequency.[2]

0 (DISABLED): Event Monitor/Recorder clocks are disabled. Operation of the Event Monitor/Recorder is disabled except for asynchronous clearing of GP registers if selected.

1 (ENABLE_EVENT_MONITOR16HZ): Enable Event Monitor/Recorder and select a 16 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 62.5 ms to 125 ms will be filtered out.

2 (ENABLE_EVENT_MONITOR64HZ): Enable Event Monitor/Recorder and select a 64 Hz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 15.6 ms to 31.2 ms will be filtered out.

3 (ENABLE_EVENT_MONITOR1KHZ): Enable Event Monitor/Recorder and select a 1 kHz sample clock for event input edge detection and glitch suppression. Pulses (in either direction) shorter than 1 ms to 2 ms will be filtered out.

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